NEW – Global SIPI University
ANNOUNCING THE INAUGURAL COURSE
Global Signal Integrity and Power Integrity (SIPI) University
Wednesday, August 7, 2024
Course Overview: Signal integrity (SI) and power integrity (PI) are gaining an ever-growing attention due to today’s higher data rates and larger currents in high-speed digital systems. Industries call for skilled engineers with both basic and advanced background in these two disciplines. Courses dealing with SI and PI related topics at academic level are limited and offered by only a few institutions and research laboratories in the US and worldwide. The inaugural “Global SIPI University” aims at bridging this gap with a one-day introductory course at the Electromagnetic and Signal & Power Integrity Symposium to be held in Phoenix, Arizona, from August 5-9, 2024.
The mission of the “Global SIPI University” is to provide technicians and engineers the opportunity to acquire SI and PI concepts from experienced and well-known instructors from both industry and academia. The “Global SIPI University” offers a rigorous background directly linked with practical problems and solutions. Attendees will acquire application-oriented skills and knowledge about the need for signal and power integrity analysis as well as the tools and methods available for tackling SI and PI related problems. Basic and fundamental concepts involving limited but relevant theory will be offered to fully understand how practical problems can be approached using analytical methods, simulation tools, as well as measurements to validate simulations. Instructors will discuss design examples to provide a clear insight and processes for guiding the attendee towards problem solutions.
COST: $175 Advance / $225 After Early Discount
Electrical engineers with a professional background in EMC that want to
dive into or broaden their skills in state-of-the-art signal integrity and power integrity.
MEET OUR CO-CHAIRS
Christian Schuster (IEEE Senior Member) received a Diploma degree in Physics in 1996 and a Ph.D. degree in electrical engineering in 2000. Since 2006, he is a Full Professor at Hamburg University of Technology (TUHH), Germany. Prior to TUHH he was with the IBM T. J. Watson Research Center, Yorktown Heights, NY. His current interests include signal and power integrity of digital systems, multiport measurement and calibration techniques, and development of electromagnetic simulation methods for communication electronics. He serves as an Associate Editor for the IEEE Transactions on EMC as well as an Adjunct Associate Professor at the School of Electrical and Computer Engineering of the Georgia Institute of Technology.
Francesco De Paulis (Senior Member IEEE) received the M.S. degree in Electrical Engineering in May 2008 from Missouri University of Science and Technology (formerly University of Missouri-Rolla), USA, and the Ph.D. degree in Electrical and Information Engineering in 2012 from the University of L’Aquila, L’Aquila, Italy. He is currently an Associate Professor at the Electromagnetic Compatibility and Signal Integrity Laboratory at the University of L’Aquila. His main research interests are in signal and power integrity, high speed channel design and optimization, composite materials for shielding and absorption, RF interference in mixed-signal system, TSVs in silicon chips and interposers, antenna design and measurement techniques, remote fault detection in transmission lines, microwave design of electronic devices and systems for space applications.
MEET OUR INSTRUCTORS
Albert Ruehli, Ph.D. in EE, UVM, 1972, Honorary Doctorate, Lulea University, Sweden, 2007, was a member of VLSI design and CAD at IBM Watson Research until 2009. He is now an Adjunct Professor at the Missouri University of Sci. & Tech. An editor/co-author of books and over 250 papers, he received numerous IBM Awards, the Guillemin-Cauer Prize, and the Golden Jubilee Medal in 1999. He also received the Richard R. Stoddart, and the Honorary Life Member Awards from the IEEE EMC Society.
Stephen Scearce is a Hardware Engineering Director of Cisco’s COE Electronics Packaging and Diagnostics team. Stephen provides the technical direction/leadership for Signal Integrity, Power Integrity, Mechanical/Thermal Design, ECAD, and Software Diagnostics design in US/China. Stephen has worked for Cisco for 23 years focused on ASIC/System PI, SI, Package Design, and EMC design. He holds 12 issued patents and has co-authored 17 papers. He has volunteered for the IEEE Electromagnetic Compatibility Society for the past 10 years, and is currently serving as the Society Treasurer, and the 2022-2024 EMC+SIPI Symposium treasurer. Stephen received his BSET and MSEE from Old Dominion University, Norfolk VA.
Kemal Aygün is a Fellow at Intel Corporation and manages the High Speed I/O team in the Electrical Core Competency group. He has co-authored five book chapters, more than 90 journal and conference publications, and holds 93 U.S. patents. His research interests include novel technologies along with modeling and characterization techniques for microelectronic packaging. Dr. Aygün was the General Chair of the 2020 IEEE Electrical Performance of Electronic Packaging and Systems Conference. He is an IEEE Fellow, a Distinguished Lecturer for IEEE Electronics Packaging Society (EPS), and a co-chair of the EPS Technical Committee on Electrical Design, Modeling, and Simulation.
Bhyrav Mutnury is a Senior Distinguished Engineer and Global Team Lead of Signal Integrity group at Dell Technologies, where he is responsible for designing next generation high-speed servers. He has co-advised 5 PhD students and currently co-advising 2 PhD students. He received his Doctor of Philosophy degree in Electrical Engineering in 2005 from the Georgia Institute of Technology, Atlanta, GA.
Dr. Mutnury has authored more than 100 publications in various conferences and journals. Dr. Mutnury has 250 issued patents and another 50 in the pipeline. He is currently an IEEE Fellow and the recipient of IEEE Technical Achievement Award.
Wendemagegnehu (Wendem) T. Beyene, Analog & Mixed Signal Architect, Reality Labs at Meta Platforms.
Dr. Wendem Tsegaye Beyene has been employed, in the past, by IBM, Hewlett-Packard, and Agilent Technologies, Rambus, and Intel. He has been responsible for end-to-end signal and power integrity analysis of low-power SoC, Memory, CPU and FPGA including fabric and high-speed I/O subsystems as well as I/O modeling. He is currently an Analog & Mixed Signal Architect in Reality Labs at Meta Platforms.
Dr. Beyene, an IEEE fellow, has authored or co-authored numerous refereed publications. He is currently a Senior Area Editor of IEEE Trans. on CPMT and serving as a Distinguished Lecturer for IEEE EPS and IEEE EMCS Societies
Eric Bogatin received his BS in Physics from MIT in 1976 and PhD in Physics from the University of Arizona in 1980. He has been active in the SI field for 40 years and has written 15 books and hundreds of articles in this field. Currently, he teaches SI and Electronics courses for undergraduate and graduate students. He is also a Fellow with Teledyne LeCroy and the technical editor of the Signal Integrity Journal.
Ihsan Erdin is a practicing engineer with 25 years of experience in the design of high-speed data communication circuits. He has been working as an SI SME at Celestica in the design of server and networking systems since 2007. He is also an adjunct faculty member at Carleton U. Ottawa with research interests in electromagnetics theory and microwave engineering methods in PCB applications. He holds a Ph.D. degree in electromagnetics engineering. He is a member of the Professional Engineers Ontario and a senior member of IEEE. He also served as a Distinguished Lecturer of the IEEE EMC Society.
Chulsoon Hwang is with the EMC Laboratory at Missouri S&T. He received his Ph.D. degree from KAIST, Daejeon, South Korea in 2012. From 2012 to 2015, he was with Samsung Electronics. In 2015, he joined the Missouri S&T where he is currently an Associate Professor. He has authored or co-authored 150+ IEEE journal/conference papers. His research area includes High-speed Digital System Design, RF/digital Integration (RF Desensitization), Machine Learning in Hardware Design, and Electromagnetic Interference (EMI). He was a co-recipient of 10+ Best Paper/Best Student Paper Awards from various conferences including the IEEE EMC+SIPI, the AP-EMC, and the DesignCon.
Opening: Progression of SIPI Modeling: A 50-Year Journey to Modern System Design Challenges
Albert Ruehli and Stephen Scearce
Abstract: The introductory combined presentations cover the evolution of SIPI including today’s challenges. The first part presents the evolution of the SIPI approach from its start 50 years ago. SIPI was originally driven by large high speed mainframe computer designs such as IBM’s. With time, the increase in performance of IC’s made the SIPI modeling a general necessity which resulted in new companies providing SIPI design tools. The increase in system performance brought about significant improvement of high performance in solvers with other advantages such as graphical user interfaces. In this presentation, we also describe the challenges in modern system for High-Speed Serdes design and the latest DDR5 implementations. Other issues are considered such as the large current and power delivery challenges in high performance systems.
Keynote: Global Industry Trends & Demands – Systems and Packaging Perspective
Abstract: With the emergence of new applications such as artificial intelligence, electronic systems need to provide increasingly improved performance. One area where the performance demand has been scaling very aggressively is for interconnecting different components in a system with high-speed/high-bandwidth signaling. This presentation will review some of the recent global trends and demands in this area, from both a systems and a packaging perspective. Emergence and evolution of ‘system-in-package’ architectures, corresponding interconnect technologies, and some key SI/PI challenges will be described. Finally, some recent advances on standardization of on-package high-speed signaling interconnects, that complement existing system-level standards will also be discussed.
Signal Integrity I: High-Speed Signal Integrity Challenges for Next Generation
Abstract: The challenges associated with high-speed signal integrity (SI) are becoming exponentially complex with the doubling of signal speeds every generation. In this presentation, high-speed server design is used an example to demonstrate the next generation SI challenges and potential opportunities to overcome these challenges. The presentation covers basics of SI, high-speed interconnects, analog and digital equalization and high-speed challenges beyond 32 Gbps. The presentation also touches up some AI/ML use cases for next generation challenges.
Signal Integrity II: Electrical Signaling—Modulation, Equalization, and Channel Design
Abstract: The presentation explores different modulation and signaling techniques with the goal to achieve over 224-Gb/s link speed through electrical signaling. The focus of this work spans from interconnects to transceiver architecture from system, channel and signaling point of view. In addition to traditional multilevel signaling pulse amplitude modulations (PAM-4, PAM-8, ···), this talk also compares simultaneous bidirectional signaling and multiwire encoding techniques as potential solutions for even higher data rates. These signaling options are compared both from performance and implementation complexity point of view with possible improvements required to further extend the speed and reach of electrical signaling.
Signal Integrity III: Signal Integrity Measurements and Simulation
Abstract: Measurement and simulation go hand in hand in any efficient design workflow. Simulation is used in both the pre-layout phase to establish accurate design rules and in the post-layout design phase to establish confidence in a design before committing large resources to the hardware. Measurements are critical to validate simulation processes and device or component models and characterize materials used as input to the simulation. This course will provide an introduction to some of the measurement and simulation tools available for SI/PI and EMI applications.
Power Integrity I: Fundamentals of Power Integrity with Practical Analysis Techniques for Current and Emerging Designs
Abstract: Fundamental issues of PI will be laid out from a perspective with its direct relation to SI. The role of ground vias in multilayered boards will be explained in some practical PCB stackups. Basic decoupling concepts will be covered with placement and selection of bypass capacitors including the effects of interplane capacitance. Insights will be provided to inner workings of simulation methods for their efficient use in PI analysis and optimization. Practical PCB decoupling methodologies will be presented and challenges will be discussed for the emerging 100+ Gb/s designs including substrate decoupling of co-packaged optics and embedded discretes.
Power Integrity II: VRM, package/IC-level PDN Design
Abstract: Continuing from PI I, the basic elements of a PDN, including on/off-chip VRM and package/IC-level PDN, along with their roles in power integrity, will be presented using practical examples. Additionally, challenges and research trends in recent PDN design will be introduced.
Closing Session: The Future of SI & PI Engineering – Open discussion with all instructors and attendees.
Moderators: Christian Schuster and Francesco de Paulis